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Nanosilicon dot arrays with a bit pitch and a track pitch of 25 nm formed by electron-beam drawing and reactive ion etching for 1 Tbit/in.2 storage

机译：通过电子束拉伸和反应离子刻蚀形成的1比特/英寸2存储的位距和轨道距为25 nm的纳米硅点阵

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Hosaka, Sumio; Sano, Hirotaka; Shirai, Masumi; Sone, Hayato;
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年度 2006
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1. Nanosilicon dot arrays with a bit pitch and a track pitch of 25 nm formed by electron-beam drawing and reactive ion etching for 1 Tbit/in.~2 storage [J] . Sumio Hosaka, Hirotaka Sano, Masumi Shirai, Applied Physics Letters . 2006,第22期

机译：通过电子束拉伸和反应性离子刻蚀以1 Tbit / in。〜2的存储率形成的位距和轨道距为25 nm的纳米硅点阵
2. Nano-dot arrays with a bit pitch and a track pitch of 25 nm formed by EB writing for 1 Tb/in~2 storage [J] . Sumio Hosaka, Hirotaka Sano, Masumi Shirai, Microelectronic Engineering . 2007,第5a8期

机译：通过EB写入以1 Tb / in〜2的存储形成的位距和轨道间距为25 nm的纳米点阵列
3. Nano-dot and -pit arrays with a pitch of 25 nm × 25 nm fabricated by EB drawing, RIE and nano-imprinting for 1 Tb/in~2 storage [J] . Sumio Hosaka, Zulfakri Mohamad, Masumi Shirai, Microelectronic Engineering . 2008,第5a6期

机译：通过EB拉丝，RIE和纳米压印制造的间距为25 nm×25 nm的纳米点和坑阵列，用于1 Tb / in〜2的存储
4. 25nm pitch master and replica mold fabrication for nanoimprinting lithography for 1Tbit/inchsup2/sup bit patterned media [C] . Hideo Kobayashi, Shuji Kishimoto, Kouta Suzuki, Alternative lithographic technologies IV. . 2012

机译：用于1Tbit / inch ^{2 位图案化介质的纳米压印光刻的25nm间距母版和复制品模具制造}
5. Actual information storage with a recording density of 4 Tbit∕in.2 in a ferroelectric recording medium [O] . Kenkou Tanaka, Yasuo Cho -1

机译：实际信息存储在铁电记录介质中记录密度为4 Tbit / in.2
6. Actual information storage with a recording density of 4 Tbit∕in.2 in a ferroelectric recording medium [O] . Tanaka, Kenkou, Cho, Yasuo 2010

机译：实际信息存储在铁电记录介质中，记录密度为4 Tbit / in.2

Nanosilicon dot arrays with a bit pitch and a track pitch of 25 nm formed by electron-beam drawing and reactive ion etching for 1 Tbit/in.2 storage

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